NEED EXPERT FOR COMPUTER ENGINEER final

COMPE375 Exam4 – 2 1 – EEPROM Programming [30 pts] Assume that we feel a microcontroller that has a byte-addressable EEPROM with a bulk of 128 bytes. You feel the subjoined span offices to interface with this EEPROM part: • uint8_t eeprom_read(uint8_t* addr): This office reads the deviation of the harangue precipitation “addr” and produce the deviation as a uint8_t unsteady. • empty eeprom_write(uint8_t* addr, uint8_t input_data): This office transcribes the uint8_t unsteady “input_data” (relieve inarrange parameter) to the harangue precipitation “addr” in the EEPROM. Using the over cognomen, transcribe down a office, using the prototype under, that does the subjoined: i. The office reads the resigned of the precipitation that has the meanest harangue in this EEPROM part and abundances it in a uint8_t unsteady determined var1. ii. If the prize of var1 can be a operative harangue in this EEPROM part, the office reads the deviation of the retention precipitation that can be modeed by var1 as the harangue and abundances the resigned in a uint8_t unsteady determined var2. iii. If the prize of var1 canreferable attributable attributable attributable be a operative harangue in this EEPROM part, the office reads the resigned of the retention precipitation that has the biggest harangue in this EEPROM and abundances the resigned in a uint8_t unsteady determined var2. iv. If var1 is strictly important than var2, the office transcribes var1 to the retention precipitation that has the biggest harangue. v. If var1 is strictly smaller than var2, the office transcribes var2 to the retention precipitation that has the meanest harangue. empty myOffice (){ /* Here, past this EEPROM is byte-addressable and its bulk is 128 bytes, it has 128 likely harangue precipitations, 0 – 127. The meanest harangue is 0, and the biggest harangue is 127. However, a uint8_t unsteady can obtain prizes unmoulded 0 – 255. If a uint8_t unsteady is important than 127, it canreferable attributable attributable attributable be a operative harangue in this EEPROM. */ uint8_t var1; uint8_t var2; var1 = eeprom_read((uint8_t*) 0); //meanest harangue is 0 if (var1 < 128) //if var1 < 128, then it can be a operative harangue var2 = eeprom_read((uint8_t*) var1); else var2 = eeprom_read((uint8_t*) 127); //biggest harangue is 127 if (var1 > var2) eeprom_write((uint8_t*) 127, var1); else if (var1 < var2) eeprom_write((uint8_t*) 0, var2); } COMPE375 Exam4 – 3 2 – Embedded Retention Architectures and Retention Organization [30 pts] a) Assume that we feel an SRAM retention morsel with 48 pins. In this morsel, the strength and administer pins are doubled to prepare safety coercion possible failures. If this morsel has a engagement bulk of 4-bits (each harangue tarrys 4 bits of postulates), what is the acme bulk of this retention morsel in bytes? [15 pts] Past this is an SRAM retention, normally we would demand at smallest 2 strength and 3 administer pins. Past strength and administer pins are doubled to prepare safety, we demand 4 strength and 6 administer pins. Furthermore, the sum of required postulates pins is 4 past the engagement bulk is 4 bits. This leaves us 48-4-6-4 = 34 bits coercion harangue pins. Thus, the aggregate sum of haranguees becomes 234 = 24×230 = 16G. Each harangue precipitation tarrys 4 bits, so the aggregate distance is 16G x 4 bits = 64Gbit = 8GB. b) Can a scheme feel SRAM as the simply airy retention? Compare the practices and disadvantages of such a contrivance resolution. [7 pts] Yes, a plan can feel SRAM as the simply airy retention, e.g. your AVR plan uses SRAM to appliance records and the ocean retention. It does referable attributable attributable attributable attributable attributable attributable attributable attributable attributable feel a DRAM. The practice of such a contrivance is that any retention mode would be very firm past there is no DRAM. However, past SRAM is high-priced and referable attributable attributable attributable attributable attributable attributable attributable attributable attributable distance-efficient, the whole of SRAM that can be arrange on a morsel is very-much scant, e.g. your AVR plan has simply 2KB SRAM. c) We perceive that EEPROM and Flash are twain non-volatile. Why would a microcontroller (e.g. your AVR plan) feel twain of them profitable in a morsel, equable though natural distance is very scant? Specifically illustrate what you can perform by having multiple non-airy retention types in a solitary microcontroller morsel. [8 pts] In a microcontroller, non-airy retention is required to tarry the program legislation (instructions etc.), any steady, read-simply postulates unmoulded an effort, and postulates that demands to abide over multiple efforts. Flash retention is good-natured-natured coercion tarrying the program instructions as it is byte-programmable and block-erasable (this prepares prolific obliteration unmoulded span program downloads). However, if you demand to abundance single unsteadys that demand to abide (such as program unsteadys, scheme unsteadys/constants), Flash retention becomes inprolific past the obliteration is referable attributable attributable attributable attributable attributable attributable attributable attributable attributable in bytes. EEPROM prepares an prolific practice to abundance this peel of unsteadys. On the other agency, EEPROM is more high-priced than Flash, thus it is referable attributable attributable attributable attributable attributable attributable attributable attributable attributable cost-prolific to raise a scheme with simply EEPROM. Thus, a microcontroller unconcealedly chooses to feel twain of them to prepare options coercion the programmer. COMPE375 Exam4 – 4 3 – Modeling [40 pts] • Petri Inveigles [25 pts] Given the under Petri Inveigle and moderate marking [P1, P2, P3] = [1,0,0]: i. Draw the reachability graph. [10 pts] ii. Answer the subjoined questions. [15 pts] • Is the inveigle limited? _____no______ [2 pts] • Is the inveigle unrepealed? _____no______ [2 pts] • Is the inveigle undefiled? _____no______ [1 pts] • What is the liveness of each transition? [3 pts each] i. t1: L3 (Series S0 – infinite t1s) ii. t2: L1 (In any series, t2 is done at most unintermittently) iii. t3: L2 (Using the unconcealed series coercionmula Sn, coercion any prize n, we can perceive a series where t3 is done n times, beside never infinitely) • What is the liveness of the inveigle? L1 (smallest order unmoulded the transitions) [1 pts] P1 P2 P3 t1 t2 t3 COMPE375 Exam4 – 5 • State Machines [15 pts] Convert the subjoined StateChart to its equiponderant Finite State Machine (FSM) justice. Solution:

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